Specialisation:

• Algorithms for Physical Design Automation of ICs
• Synthesis of Quantum Circuits
• Hardware and IoT security

Major Professional Contributions:

My seminal contributions have been in algorithms for design automation with three major facets, in each of which I have been a pioneer in India.

• The earliest distinctive accomplishments are multi-objective optimization in physical design, particularly floorplanning, placement and routing, for a gamut of nanotechnology nodes, lithography generations and IC design styles. Fundamental insights into inherent nonslicibility in floorplans, placement and floorplan optimization for ASICs and FPGAs have led to several publications in top-tier international journals and peer-reviewed conference proceedings over the years. Novel algorithms for FPGA floor planning have inspired leading EDA companies to consider adopting the methods in their software tools. Further, works in test pattern generation methods for new types of circuit marginality, such as timing faults due to power supply droop, have led to very successful industry sponsored research collaborations.

• In the recent salient area of design for security, I have contributed to design methodologies for not only hardware intellectual property (IP) but also sensor-based medical informatics such as systematic poisoning attacks and defenses for biomedical machine learning. Another work on healthcare sensor based continuous authentication has led to a US patent. My co-edited book on IP and SoC Security has been a best-selling technical volume.   

• In the emerging paradigm of quantum computing, with my research scholars I have devised new algorithms for efficient synthesis of quantum logic circuits which include quantum error correction.  We have also carried out proof-of-concept research on synthesis methodologies for multi-valued, namely ternary and quaternary quantum logic.

• My credentials as a researcher are captured in my Google Scholar publication record and associated citation count (> 1446) and my DBLP.  I have co-authored three successful edited books, three book chapters and a US patent.

Consultancy Areas:

• Quantum circuit optimisation - with IBM India Research 
• Design for Manufacturability - with IBM research
• Circuit marginality and test pattern generation - with Intel USA
• Testing of asynchronous circuits - with Strategic CAD Labs, USA.

Sector Associated With:

• Algorithms for design automation of ICs
• Quantum circuit optimisation for near-term noisy intermediate scale quantum devices
• IoT security

Sectors Interested to Offer Service:

• IoT based health monitoring in difficult terrains
• 3D image reconstruction for anomaly detection

Professional Experience

• One of the primary areas of my research has been algorithms for design automation in integrated circuits (ICs), particularly in the area of physical design, which lie at the core of most modern technological advances. My work on placement and floorplan optimization started as part of my graduate study at MIT USA and subsequent doctoral dissertation work. Fundamental insights into inherent non-slicibility of layouts for general and FPGA placement and floorplan optimization has led to several publications (IEEE TCAD, IEEE TVLSI, ACM TODAES, ACM TECS, DAC, ICCAD, ICCD, ISVLSI, VLSI-SoC etc. over the years) and a book chapter in the Handbook. My published works on algorithms for FPGA floorplanning have inspired leading EDA companies to consider adopting the methods in their software tools. My work on fault modelling and test pattern generation for new types of circuit marginality, such as timing faults due to power supply droop, have led to very successful sponsored research collaborations.

• As Principal Investigator, I have successfully completed research projects on important problems sponsored by leading industries such as Intel Corp., IBM, TI.

• In the important area of IP and SoC security, my focus has been on design for security in not only IC chips and SoCs but also in health care informatics and IoT. One of my contributions on systematic poisoning attacks and defenses for biomedical machine learning (IEEE J-BHI, 2015) is of very significant interest to leading companies who are investing heavily in secure biomedical services. 

• The third field in which I have been conducting research with my research scholars is algorithmic synthesis of Quantum Circuits. The works span methodologies for both technology independent and dependent stages of the design flow, The unique constraints of quantum computing technology such as resource minimization and quantum error correction hardware have been considered in her work on physical design for this new paradigm of computing, resulting in publications (Physical Review A, TVLSI, ISMVL, RC, Engineering Letters) that are already very well cited. I have also carried out proof-of-concept research on synthesis methodologies for multi-valued, namely ternary and quaternary quantum logic.

• As a teacher, I have delivered numerous invited talks and tutorials. I have also undertaken very effectively several academic administrative responsibilities delegated to her.

• I have been serving on Steering Committees, technical programs and organizing committees of many international conferences and symposia, as well as on Editorial boards of top journals. I was the prime mover in starting the IEEE CAS Society Chapter in the Kolkata Section and the Founding Chair of the first chapter of IEEE CEDA in India.

Keywords

• Research in algorithms for physical design automation of ICs
• Synthesis of quantum circuits for NISQ devices
• Hardware security
• IoT security